Typical implementations of multi-chip circuits generally require that certain functions of the various chips be performed at specific times or within specific time frames. Generally there may be timing circuitry associated with the multi-chip circuit that provides a timing signal to one or more of the chips in the circuit. Maintaining consistent timing between chips in a multi-chip circuit can present problems that may require relatively costly solutions. The requirement for consistent timing becomes all the more profound when the chips have a tight timing budget and/or high speed operation of the chips is needed. A non-limiting example includes the use of double data rate (“DDR”) chips.
Compensating for timing variations that occur between chips are typically handled in various ways, such as by supplying a clock signal to each chip, providing a phase lock loop (“PLL”) or a delay-locked loop (“DLL”) to certain chips in the circuit, or providing a digitally controllable delay line (“DCDL”) that is calibrated through clock and data training with built-in self test circuitry. These solutions are not attractive since they are costly, add unnecessary complexity, and/or require a relatively large amount of power. These solutions are even more unattractive when the multi-chip circuit is a low-power circuit such as for low-power e-DRAM chips.
Multi-chip circuits may include 2.5D or 3D architectures or 3D chip stacks (sometimes referred to herein as “3D stack”, “3D IC”, “stack of dies”) which encompass architectures where chips are positioned on more than one plane and may be integrated both horizontally and vertically into a single circuit, such as a system on a chip. These multi-chip arrangements may also include a through-silicon via (“TSV”) or interposer, as is known in the art. Additionally, 3D ICs also encompass the situation where there exists more than one vertical stack of chips in the circuit. Furthermore, the chips in a 3D IC may be of different varieties, such as, but not limited to, processors, memory (of various types and capacities), digital signal processors (“DSP”), radio frequency (“RF”) modules, etc., as would be familiar to those of skill in the art.